I am slowly working my way through the unimplemented instructions. Another bunch is done, here are the details of the recent update:
- Implementation of flag condition "addressing" modes.
- Implementation of ST.B Dx, SF.B Dx, Scc.B Dx, ST.B mem, SF.B mem, Scc.B mem, PEA.x, MOVE.x #imm,mem, CLR.x Dy, CLR.x mem and LEA instructions.
- Fixed BTST instruction: testing bits higher than 15 was wrong.
- Merged multiple condition code-related lines in the 68k instruction descriptor table.
- Removed unnecessary parameter load for cache_miss function from the translated code PC verification code.
- Added cache miss check for normal execute handler.
- Code cleanup: removed the TODO label from immediate addressing modes used as destination and added meaningful error message instead.
- Removed ignored parameter from the unsupported opcode macroblock push function.
The highlight of this change set is the implementation of the flag checking "addressing" modes. These are not real addressing modes; more like a simple way of implementing the numerous conditional instructions which are checking the arithmetic flags.
This important change opens the gate for the conditional branching instructions (Bcc and DBcc), that are essential for any average loops and iterations. For now only the conditional set instructions are implemented, because it was much more easy to test these.
I also took some weekday nights for dealing with some simple instructions, like LEA, PEA and CLR. On the working days I am too tired, this is all I can afford.
There is still no fix for the OS booting issue. I have tried to trace it again, at least now found out it is not about the simulated cache manipulation, because there is no cache-incoherency detected. I am still puzzled by this whole problem.