Found potential race condition on writes
After looking at datasheets for the 273 latches used and 74act74 flipflop used, the worst case propagation delay is something like 12.3ns.
But my NAND gate ACT00 logic which is triggered by the same CAS signals has a lower propagation delay of between 1-9ns.
So despite a 0ns setup time, it’s possible that I’m violating the SRAM setup times during a write by dropping /CE before the addresses have stabilized into the memory.
I haven’t come up with a solution yet, but it will likely involve adding an additional gate or two to increase the propagation delay.